This piece builds on our earlier coverage, "Neuromorphic Chips and the Future of Edge AI," which laid out the architectural promise of spike-based silicon. Here we examine the accelerator engineering: how the hardware exploits sparsity, what it has actually measured, and where the efficiency argument holds or breaks.
Why "Revival" Is the Right Word
Neuromorphic computing isn't new. Its lineage runs back to Carver Mead's analog VLSI work in the late 1980s, and spiking neurons have lived in academic hardware for decades. What's different now is that three separate curves have converged.
The first is algorithmic. Spikes are non-differentiable, so standard backpropagation doesn't apply to SNNs cleanly, and training was long the field's weakest link. Surrogate-gradient methods and ANN-to-SNN conversion have closed much of that accuracy gap. Spiking versions of transformers now exist too, beginning with Spikformer in 2022, which showed that self-attention can be made spike-compatible.
The second is silicon diversity. This is no longer a story about a handful of proprietary research chips. FPGA-based SNN accelerators are a routine publication category, and a fully open-source SNN ASIC has been taped out on an open process design kit.
The third is deployment pressure. Wearables, event cameras, keyword spotting, and drone perception all run under tight power and latency budgets. Those constraints create demand for inference hardware that only works when there's something to work on.
The Core Argument: Compute Only When a Spike Happens
Every SNN accelerator rests on one architectural claim. SNN activations are sparse events — binary, or low-precision integers — rather than dense floating-point tensors. Hardware built around them should spend energy only when a spike occurs. A conventional accelerator reads memory and toggles logic on every cycle whether or not an activation carries information. An event-driven design, in principle, doesn't.
The strongest version of this pairs an event-driven accelerator with an event-driven sensor. A Prophesee EVK 3.0 Event-Based Camera Kit triggers when a pixel's brightness changes, so the whole pipeline, from photodiode to classifier, runs on events rather than frames.
The field's own reviewers are careful not to overstate it. In To Spike or Not To Spike (2023), Ottati, Gao, Chen, Brignone, Casu, Eshraghian, and Lavagno ran a quantitative comparison of digital acceleration techniques for ANNs and SNNs and reached three conclusions:
ANNs currently process static data more efficiently.
Neuromorphic sensors — event cameras and silicon cochleas — deserve further investigation as a natural match for SNNs.
Hybrid SNN/ANN approaches are a promising direction.
That first finding matters because so much SNN hardware is benchmarked on MNIST and CIFAR-10, static datasets where the spiking model has no structural advantage. The practical question for anyone evaluating this hardware isn't "are SNNs more efficient than ANNs?" It's whether your input data is sparse and event-driven in the way the hardware assumes.
What the Accelerators Look Like
FPGAs as the proving ground
Reconfigurability makes FPGAs the default place to try a new SNN architecture before anyone commits to a tape-out.
Spiker implements Leaky Integrate-and-Fire neurons — the standard spiking neuron model — on a Digilent Nexys A7 Artix-7 FPGA Development Board. Other designs target DVS classification specifically, combining structured sparsity with an early-stop mechanism that halts computation once the classification is settled. That's latency pulled out of the time dimension of spiking inference, not just the spatial one.
FireFly-S, from Li, Li, Shen, Zhao, Zhang, and Zeng, targets sparsity on both sides of the multiply. On the software side, gradient rewiring pushes weight sparsity past 85% and quantization takes weights to 4 bits. On the hardware side, bitmap-based decoding locates non-zero weights and input spikes so the datapath skips everything else. Reported efficiency is 10,047 FPS/W on MNIST, 3,683 FPS/W on the event-based DVS-Gesture dataset, and 2,327 FPS/W on CIFAR-10. The work was accepted to IEEE Transactions on Circuits and Systems I.
Some designs trade generality for tractability on purpose. SeaSNN, a lightweight spiking attention accelerator for FPGAs, implements channel-wise attention instead of modeling complex temporal dependencies, keeping comparable accuracy benefits at much lower computational overhead.
Object detection shows the same co-design pattern. Spiking neural networks are too large for real-time FPGA deployment as published. A 2024–2025 FPGA accelerator closes that gap with channel pruning, batch-normalization fusion, and scale-aware pseudo-quantization. The contribution isn't the chip or the model alone — it's the negotiation between them.
OpenSpike: a tape-out without a proprietary toolchain
OpenSpike, from Modaresi and colleagues, is an SNN accelerator built entirely with open-source EDA tools, an open process design kit, and memory macros generated with OpenRAM, taped out on SkyWater's 130 nm process. It holds over a million synaptic weights in a reprogrammable architecture, runs at 40 MHz and 1.8 V, uses a PicoRV32 RISC-V core for control, and occupies 33.3 mm². Reported throughput is 48,262 images per second at a wall-clock time of 20.72 µs, and 56.8 GOPS/W.
Its neurons use hysteresis to set an adaptive threshold — effectively a Schmitt trigger — which reduces state instability. The design files are public on GitHub.
The throughput matters less than the process. A working neuromorphic accelerator now exists that anyone can inspect, modify, and resubmit without a commercial EDA license or a proprietary process design kit.
An earlier benchmark, and what it measured
A 2020 asynchronous reconfigurable SNN accelerator put 1,024 neurons and one million synapses on bundled-data asynchronous circuits, with multicast communication across a mesh network and an event-driven time-step update. It reached 98% accuracy on MNIST at better than 1 GIPS/W, which the authors put at 32 times the prior state of the art. It's a useful marker of how fast efficiency figures have moved. It's also an MNIST result, and by the 2023 review's finding, that's the kind of benchmark where spiking hardware has the least to prove.
Hybrids: spiking as a co-processor
A 2025 power-efficient hybrid CNN-SNN accelerator doesn't convert whole networks. It converts only the most energy-intensive layers into spiking form and leaves the rest as conventional continuous-valued computation, reconfiguring adaptively.
That design choice cuts against the framing of neuromorphic chips as a replacement for conventional accelerators. SNN blocks are being placed where activation sparsity is highest, alongside dense accelerator IP rather than instead of it. It's also the direction the 2023 review pointed to.
Loihi 2: The Reference Research Architecture
Intel's Loihi 2 is the chip most SNN research benchmarks against, extends, or writes software for. It's a research processor, not a commercial part, but its design sets the vocabulary.
Announced in September 2021, Loihi 2 was built on a pre-production version of the Intel 4 process using EUV lithography. The die is 31 mm² with roughly 2.3 billion transistors, organized into 128 neuromorphic cores that pass spike messages over a network-on-chip. Each core occupies 0.21 mm² and supports up to 8,192 neurons, for up to 1 million neurons and 120 million synapses per chip.
Three architectural choices stand out:
Graded spikes. Loihi 2 carries integer-valued spikes as well as binary ones, at an insignificant additional energy cost. That narrows the representational gap between spiking and conventional low-precision networks.
Programmable neuron state. Neuron models can use up to 4,096 states, up from 24 on the original Loihi, so the chip isn't locked to a single spiking neuron model.
Flexible connectivity. Cores support dense, sparse, and convolutional synaptic topologies, plus factorized and stochastic connections.
Intel's own comparison against first-generation Loihi claims up to 10× faster processing and up to 15× greater resource density. Early evaluations showed more than 60× fewer operations per inference on Loihi 2 than standard deep networks running on the original Loihi, without accuracy loss.
For scale, the original Loihi, described by Davies and colleagues in IEEE Micro in 2018, was a 60 mm² chip on a 14 nm FinFET process with 2.07 billion transistors, 33 MB of SRAM, 128 neuromorphic cores, and three x86 cores, supporting up to 130,000 neurons and 130 million synapses.
Intel released Lava alongside Loihi 2 as an open-source software framework for neuro-inspired applications. In April 2024, it announced Hala Point, deployed at Sandia National Laboratories: 1,152 Loihi 2 processors in a six-rack-unit chassis, supporting 1.15 billion neurons and 128 billion synapses at a maximum of 2,600 W.
Loihi has also changed what researchers thought neuromorphic hardware could learn. Los Alamos National Laboratory researchers showed that backpropagation — long assumed to be impractical on neuromorphic architectures — can be realized efficiently on Loihi. On-chip learning doesn't have to be limited to simpler, biologically inspired rules.
From Research Chip to Product: BrainChip Akida
Loihi 2 is the research frontier. BrainChip's Akida is the part you can buy.
In a 2025 study, Putra, Wickramasinghe, and Shafique built a deployment methodology — compatibility analysis, mapping, and on-chip learning — around the commercially available Akida v1.0 (AKD1000). The chip is fabricated on TSMC 28 nm and runs at 300 MHz, and the test system hosted it on a Raspberry Pi Compute Module 4 over PCIe. They chose Akida specifically because it supports on-chip learning for fine-tuning SNNs.
The measured results:
Image classification: under 50 ms inference latency
Real-time object detection in video: under 200 ms
Keyword recognition: under 1 ms inference, and under 2 ms for on-chip learning
Power and energy: under 250 mW of processing power and under 15 mJ of energy
On-chip learning means the device adjusts its weights locally, with no round trip to a cloud training pipeline — and for keyword recognition, that update finishes in under 2 ms.
Compared with our earlier neuromorphic coverage, this is a change in the kind of claim being made — from architectural promise to measured latency and power on commercially available silicon. The limits of the measurement matter as well. These are three workload categories on one chip, run on a 28 nm process. They make a strong case for matched workloads, not a general efficiency claim across edge inference.
Independent Comparisons Are Starting to Appear
Most efficiency figures in this field come from the chip's designers or the paper's authors. That's normal for an emerging area, but it makes independent head-to-head work valuable.
Smith, Seekings, Mohammadi, and Zand ran one such comparison in 2024: real-time facial expression recognition on the original Intel Loihi versus a Raspberry Pi 4, an Intel Neural Compute Stick, an NVIDIA Jetson Nano, and a Google Coral TPU. Loihi delivered roughly two orders of magnitude lower power dissipation than the edge AI accelerators, with comparable accuracy and real-time performance.
That's one task on first-generation silicon, not a verdict. But it's the kind of measurement — same task, same accuracy bar, different hardware — that buyers need and that most SNN papers don't provide.
The Frontier: Spiking Transformers
The open question with the largest consequences is whether spiking computation extends to transformers, and through them to the models that dominate current AI workloads.
Two 2025 accelerator papers take it on directly.
FireFly-T, from the FireFly-S team, pairs two engines inside an overlay architecture: a sparse engine that exploits activation sparsity, and a binary engine tuned for spiking attention. Against the FireFly v2 and SpikeTA accelerators, it reports 1.39× and 2.40× higher energy efficiency, and 4.21× and 7.10× greater DSP efficiency.
Bishop, from Xu, Yin, Iyer, and Li, introduces a Token-Time Bundle data structure for spiking transformer activations. It routes work between dense and sparse processing cores based on activation density, and adds a training method that increases sparsity plus an error-bounded pruning method for attention layers. It reports a 5.91× speedup and 6.11× better energy efficiency than previous SNN accelerators, with higher accuracy across multiple datasets.
Bishop's dense-and-sparse core split is the hybrid pattern again, now at the transformer layer.
The language-model result goes further. Abreu, Shrestha, Zhu, and Eshraghian adapted a 370M-parameter MatMul-free language model for Loihi 2, using the chip's low-precision, event-driven, stateful processing. The quantized model reached 3× higher throughput with 2× less energy than transformer-based LLMs on an edge GPU, with no accuracy loss from quantization. The work appeared at an ICLR 2025 workshop.
Speculation: Taken together — spiking-attention accelerators on FPGAs and a sub-billion-parameter language model running efficiently on neuromorphic silicon — these results point toward lightweight, spike-driven language and multimodal inference under strict edge power budgets. Nothing here shows that at production scale. The model is small, the platform is a research chip, and the comparison is against an edge GPU rather than a dedicated NPU. Read it as a research trajectory, not a shipping capability.
Beyond the Chip: Neuromorphic Principles in the Wireless Link
Most of this literature is about the chip. One 2024 line of work applies neuromorphic principles to the communication link in device-edge split inference.
In device-edge co-inference, a task is partitioned: the device collects and partially processes data, and a remote server finishes the job. The proposed neuromorphic wireless co-inference system runs the device's sensing, processing, and communication units on neuromorphic hardware while the server keeps conventional radio and computing. Its design criterion is transmitter-centric and information-theoretic, built on a directed information bottleneck. The goal is to cut communication overhead while keeping the information that matters for the end task, instead of shipping raw sensor data.
Speculation: If neuromorphic edge devices multiply, they'll need to exchange spike-formatted data over constrained links, and that creates pressure for shared conventions on event encoding and transport.
A Longer Horizon: Spiking Networks and Quantum Annealing
At the Loihi 2 launch, Los Alamos researcher Dr. Gerd J. Kunde described the lab's work on trade-offs between quantum and neuromorphic computing, including "exciting equivalences between spiking neural networks and quantum annealing approaches" for hard optimization problems.
Speculation: If those equivalences hold up, neuromorphic accelerators could act as classical, room-temperature stand-ins for some quantum-annealing-style optimization problems — useful where a quantum annealer is impractical but the problem structure is similar. This rests on a single lab's reported finding, and it's the most distant thread in this article.
What This Means for Anyone Evaluating the Hardware
The evidence supports a narrower claim than "neuromorphic chips will replace edge AI accelerators," and a more useful one.
Match the workload. The advantage shows up where input is temporally sparse or event-driven: DVS event cameras, keyword spotting, audio, biosignals. On static frame-based workloads, conventional ANN accelerators currently hold the efficiency edge.
Expect hybrids. The direction across FPGA hybrids, Bishop's dense and sparse cores, and the 2023 review is spiking blocks placed where sparsity is high, next to dense compute — not a wholesale swap.
Separate products from research platforms. Akida is a buyable part with measured millisecond-and-milliwatt figures for specific tasks. Loihi 2 is a research platform with graded spikes, programmable neuron models, and demonstrated on-chip backpropagation, which is capability most commercial chips don't expose.
Discount self-reported numbers. Independent same-task comparisons exist, but they're still rare. Headline efficiency figures are directionally credible, not settled.
And OpenSpike means the cost of experimenting with this hardware category has dropped. Over the next several years, that may matter more to the pace of work in this space than any single chip announcement.
This article extends our earlier "Neuromorphic Chips and the Future of Edge AI." Several threads here are set up for dedicated follow-ups: keyword spotting at sub-milliwatt power as the clearest near-term fit for event-driven silicon; event-based vision sensors and the compiler toolchains that map spiking networks onto them; and whether spiking transformers and MatMul-free language models can bring language-model capability to power-constrained edge devices.